The present invention relates to neuromorphic hardware, and more specifically, to writing, storing, and reading data using neural computation in neuromorphic hardware.
In the era of heterogeneous computing, it is anticipated that programmers will either be domain experts or sophisticated computer scientists, because few domain experts have the time to develop performance programming skills and few computer scientists have the time to develop domain expertise. The computer scientists will create frameworks and software stacks that enable domain experts to develop applications without needing to understand details of the underlying platforms.
Some of the potential benefits of heterogeneity over current practices include, but are not limited to, more efficient use of memory bandwidth, more performance per area, more performance per watt, fewer modules, boards, racks, etc.
Neural computation and neuromorphic hardware are one example of a domain specific computing approach, improving performance per watt over traditional von Neumann approaches.
Within this context, many neural computations require the ability to store, retrieve, reset, and update information at both regular and irregular intervals. For example, this may include storing a video frame, and retrieving it multiple times to perform a different operation at each retrieval, or storing a sound clip and retrieving it multiple times at the request of a user (e.g., to replay the sound clip, to perform some signal processing operation on the sound clip, etc.). At the same time, the control signals for retrieving, resetting, and updating the information may arrive at non-deterministic intervals. Moreover, short-term memory mechanisms play an extremely important role in some of the best performing neural-inspired object recognition systems.
Standard von Neumann architectures are naturally suited for storing data in memory. A typical sequence of operations may include, but is not limited to, copying data to random access memory (RAM), transferring the data from the RAM via a bus to the central processing unit (CPU), and processing the data using the CPU. This sequence of events may be repeated many times over.
In other words, the distinction between memory and processing unit is a distinguishing factor in the von Neumann architecture. However, the distinction between memory and processing unit is not so clear cut in neuromorphic architectures, making the solution to this task difficult to solve. This hinders the ability to create a hybrid/heterogeneous programming paradigm for enabling a von Neumann architecture to communicate and interact with a non-von Neumann architecture. Any non-trivial application requires modules for a form of short-term/working memory. The negative effects associated with the lack of a mechanism for storing and retrieving information is only exacerbated in a hybrid programming environment.
A memory mechanism is extremely rare in classical, non-spiking neural networks. Usually such mechanisms are implicit and do not permit resetting or querying the contents at non-deterministic intervals. In spiking neural networks, no known mechanisms implemented in hardware are known.
For heterogeneous computing applications, one option may utilize storing data in a von Neumann architecture's RAM and transfer the data to the neuromorphic hardware as needed. This has the drawback associated with von Neumann architectures, namely the high power cost associated with transferring information from RAM via a bus to the neuromorphic architecture. Thus, there are no known options available for constructing low power heterogeneous applications.